Semiconductor Fundamentals: From CMOS Design to Wafers, Oxidation, Lithography, and Doping
Whether it's a CPU or a silicon qubit, they all start from the same silicon wafer. Here we trace the manufacturing process step by step, from the basics of CMOS design through to how a single wafer becomes a chip.
The Basics of CMOS/LVS Design
Most modern digital circuits are built using CMOS (Complementary MOS) technology. By combining two types of transistors with different characteristics — NMOS and PMOS — it achieves logic circuits that draw almost no current while the signal is stable (i.e., low power consumption).
Circuit designers first design a logical circuit diagram (the schematic), then convert it into the graphical pattern actually drawn on silicon (the layout). The process of verifying that these two match correctly is called LVS (Layout Versus Schematic). It automatically extracts the circuit actually formed by the layout at the transistor and interconnect level, and checks it one-to-one against the netlist of the original schematic. In addition to this, DRC (Design Rule Check) — verifying that the layout follows manufacturing rules set by the foundry, such as minimum wire width and minimum spacing — is another step that is always performed before mask fabrication (tape-out). If either LVS or DRC turns up an inconsistency, the design can be corrected before proceeding to mask fabrication, which can cost anywhere from tens of millions to hundreds of millions of yen.
Wafer Fabrication
Everything starts with high-purity silicon (a purity level of 99.999999999% — what's called "eleven nines" — is sometimes required). Using a process called the Czochralski process, a seed crystal is dipped into molten silicon and slowly pulled upward while rotating, growing a large cylindrical single-crystal ingot.
Thin slices cut from this ingot are called wafers. At leading-edge mass-production fabs, 300mm-diameter wafers are the mainstream, and after slicing, chemical mechanical polishing (CMP) finishes them into an atomically flat mirror surface. Every subsequent process step is performed on this wafer surface.
Thermal Oxidation
When a wafer is placed in a high-temperature atmosphere of oxygen or water vapor, the silicon surface oxidizes, forming a thin, uniform film of silicon dioxide (SiO₂) — an oxide layer. This oxide layer is used as an electrically insulating layer, or as a mask that protects specific regions from doping. A particularly thin, precisely controlled oxide layer becomes the MOSFET's gate oxide itself, making it one of the most critical layers determining transistor performance.
Photoresist
A photosensitive polymer material whose chemical properties change in response to light (or an electron beam or EUV light) — photoresist — is applied to the wafer surface in a uniform thickness using spin coating. It serves as the "stencil" that determines where the pattern is transferred in the lithography step that follows.
Lithography
Lithography is the process of shining light through a mask (reticle) that carries the circuit pattern onto the photoresist-coated wafer, transferring the pattern. The wavelength of light used has grown shorter with each generation, moving from deep ultraviolet (DUV, 193nm) to extreme ultraviolet (EUV, 13.5nm) in leading-edge processes. After exposure, "development" dissolves away everything except the exposed (or unexposed) portion of the resist, completing the patterned mask.
The silicon quantum dot qubit device using High-NA EUV lithography that imec announced in May 2026 is a concrete example of an effort to improve qubit manufacturing reproducibility by further raising the resolution of precisely this lithography step.
Etching
Using the patterned photoresist as a mask, etching is the process of selectively removing the underlying material (oxide layer, polysilicon, metal interconnects, etc.) only where it is not protected by the resist. Wet etching, which involves dipping the wafer in a chemical solution, used to be the mainstream approach, but today dry etching (reactive ion etching, RIE), which removes material by bombarding it with ions in a plasma, is widely used because it achieves finer, more vertical profiles. Once etching is complete, the photoresist has served its purpose and is removed, leaving only the pattern physically etched into the wafer.
Doping
Finally, doping is the process of introducing impurity atoms into specific regions of the silicon to intentionally alter its electrical properties. Adding a pentavalent element such as phosphorus or arsenic creates an excess of electrons, producing an n-type semiconductor, while adding a trivalent element such as boron creates a deficiency of electrons (holes), producing a p-type semiconductor. In modern manufacturing processes, ion implantation — ionizing and accelerating the dopant, then implanting it at a targeted depth and concentration — is the mainstream approach; after implantation, a heat treatment called "annealing" repairs crystal damage and electrically activates the implanted impurities. This combination of p-type and n-type regions is precisely the foundation that forms the MOSFET's source and drain, and the CMOS circuit itself.
Summary
- In CMOS design, LVS verifies that the layout matches the schematic
- Wafers are made by slicing and polishing a single-crystal ingot grown by the Czochralski process
- A chip is completed by repeating the steps of oxidation, photoresist coating, lithography, etching, and doping dozens of times while building up layers
- Improvements in lithography resolution (such as EUV) are directly tied not only to CPUs but also to the manufacturing of silicon qubits
Learn How This Manufacturing Technology Is Used in Quantum Computers
Intel, imec, and Hitachi's work on silicon qubits is explained in the previous article.
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